--------------------------------------------------
-- alu.vhd
-- Sarah_Harris@hmc.edu 23 October 2005
-- 32-bit ALU used by MIPS single-cycle processor
--------------------------------------------------

library IEEE; 
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity alu is
  port(A, B:  in     STD_LOGIC_VECTOR(31 downto 0);
       F:     in     STD_LOGIC_VECTOR(3 downto 0); --SLL
		 shamt: in     STD_LOGIC_VECTOR(4 downto 0); --SLL
       Y:     inout  STD_LOGIC_VECTOR(31 downto 0);
       Zero:  inout  STD_LOGIC;  --BLEZ
		 ltez:  out    STD_LOGIC); --BLEZ
end;

architecture synth of alu is
  signal S, Bout:      STD_LOGIC_VECTOR(31 downto 0);
begin
  Bout <= (not B) when (F(3) = '1') else B;
  S <= A + Bout + F(3);

  -- alu function
  process (F(2 downto 0), A, Bout, S) begin
    case F(2 downto 0) is
      when "000" => Y <= A and Bout;
      when "001" => Y <= A or Bout;
      when "010" => Y <= S;
      when "011" => Y <= 
        ("0000000000000000000000000000000" & S(31));
		when "100" => Y <= 
		   to_stdlogicvector(to_bitvector(Bout) sll conv_integer(shamt)); --SLL
      when others => Y <= X"00000000";
    end case;
  end process;

  Zero <= '1' when (Y = X"00000000") else '0';
  ltez <= Zero or S(31);  -- BLEZ
  
end;